SV :clock signal connectivity

SystemVerilog
,
1

Hello Folks

How to check clock connectivity for below clock_control module with DUT0 DUT1 DUT2?



module clk_ctrl(en,clk0,clk1,clk2);
  
  input wire   en ;
  output wire  clk0,clk1,clk2;
  
  //wire a1 ,a2 ,a3 ;
  
  dut0 DUT0  ( .clk_b0(clk0));
  dut1 DUT1  ( .clk_b1(clk1));
  dut2 DUT2  ( .clk_b2(clk2));
  
   assign  clk0 = en ? 0 : 1;
   assign   clk1 = en ? 0 : 1;
   assign   clk2 = en ? 0 : 1;
   
endmodule

module dut0(clk_b0);
  
  input clk_b0;
endmodule 

module dut1(clk_b1);
  
  input clk_b1;
endmodule 


module dut2(clk_b2);
  
  input clk_b2;
endmodule

Thanks
Jayesh J Parmar