SV :bus driving case

SystemVerilog
1

Hi

How one can write drive logic for following bus interface such that data should be driven on WRITE cmd and should be able to read of previous READ cmd i.e clock cycle T4 -T5?

Does semaphore helps here OR clocking block should sample and drive ?

clk cycle       T1	T2	T3	T4	T5	T6
CMD             W1      W2      R1      R2      W3 	
WR_DATA         WD1     WD2                     WD3
RD_DATA		                        RD1     RD2


CMD - RD/WR
WR_DATA - 32 bit bus
RD_DATA - 32 bit bus

Regards
Jayesh J Parmar

2

Following is drive task to get same behavior.

  task drive();
   
    @(posedge clk);
       begin
         repeat(10)
              begin
              cmd<=1'b1;                           
              wr_data<=$random();
                #2 $display("[%0t] cmd=%d wr_data=%h rd_data=%h",$time,cmd,wr_data,rd_data);
              //end
         
              //begin
              cmd<=1'b0;
               @(posedge clk);
                begin
                  rd_data<=$random();
              #2;
                 end
             $display("[%0t] cmd=%d wr_data=%h rd_data=%h",$time,cmd,wr_data,rd_data);
               end
       
      end
   endtask
3

In reply to Jayesh Parmar:

You have not explained your problem well enough to help. Why would your driver need to drive rd_data? I think your bus module should be

module bus(
  input            clk,
  input            cmd,
  input      [7:0] wr_data,
  output reg [7:0] rd_data 
);
  
  reg [7:0] data;
  always @(posedge clk)  begin
    if(cmd) begin
      data<=wr_data;
    end
   rd_data <= data;
 end
endmodule
4

Thanks Dave for your reply ,I understand RTL Design code mentioned above works well.

From verification perspective ,if we want to write UVM or SV drive code ,how it will be taken care for cycle T3-T4-T5 specifically ?


clk cycle       T1	T2	T3	T4	T5	T6
CMD             W1      W2      R1      R2      W3 	
WR_DATA         WD1     WD2                     WD3
RD_DATA		                        RD1     RD2

Regards
Jayesh J Parmar