Super.Super() call alternative system verlilog

SystemVerilog
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1

I’ve a scenario like this:
Let’s say there is a base class: class A - which has a virtual function: get_data();
Then class B extended from Class A. It overrides the function get_data() and calls super.get_data() inside the overridden function.
Now, there is a class C , extended from Class B.

Requirement is to override the get_data() function in class C, however I want to directly call the Class A get_data() from inside the class C get_data() function( ideally would want to call something like super.super.get_data()) and bypass the class B get_data().

But super.super() data is not valid syntax. What could be the alternative ways this can be achieved?

2

In reply to letzask:

A::get_data()