Stuck at 1 and stuck at 0 problem

SystemVerilog
1

need to know basic concept of stuck at 1 and stuck at 0 with respect to code coverage.
can anyone specify with an example of this concept how to recognize it in code coverage tool

2

In reply to divyadm:

For detecting stuck at ‘1’ and stuck at ‘0’, doing an exhaustive walking1 and walking 0 pattern in code coverage would help. This link might help you.

http://www.amiq.com/consulting/2015/09/18/functional-coverage-patterns-bitwise-coverage/

3

In reply to smukerji:

Thank you