String generation using system Verilog

SystemVerilog
1

Dear Forum,

I am trying to generate string using SystemVerilog, the simulation is passing without error.
However the generated line number are not being updated with the needed values.

This is what I want to generate, where the values will be updated:


assign GX1F_BK[0] =  TB_0_L; 
assign GX1F_BK[1] =  TB_1_L; 
assign GX1F__BK[2] =  TB_2_L;

And this is how I am trying:


module TB();
reg [2:0] TB_0_L = 3'd1;
reg [2:0] TB_1_L = 3'd5;

wire [2:0] GX1F_BK [0:3];
generate 
    for(genvar bg=0; bg<MAX_WIDTH; bg=bg+1) begin
       assign GX1F_BK[bg] = {"TB_", $sformatf("%0d",bg), "_L"} ;
    end
endgenerate

endmodule

The simulaiton goes well, however the result of all GX1F_BK values are always 'd4.
But I expect 'd1 and 'd5.

Can you please help understand what is going here and how to make it work.

Thanks
Hayk

2

In reply to haykp:

You can’t create variable references out of strings. You could create an array for the TB_*_L regs and reference them using an index.

3

In reply to cgales:

Thanks much!