Stray coloums

SystemVerilog
,
1 
 task data_to_send (logic [3:0]index,logic [31:0]target_address='h1,logic [2:0]command='b001);
    req = i2c_sequence_item::type_id::create("req");
    //logic size;          
    //enum{write,read} dir; 
    case({ index, command})
      {4'b0100,3'b001} : begin
                           dir  = I2C_DIR_WRITE;
                           size = 5;
                         end
      {4'b1000,3'b001} : begin
                           dir  = I2C_DIR_WRITE;
                           size = 2;
                         end
      {4'b1000,3'b011} : begin
                           dir  = I2C_DIR_WRITE;
                           size = 5;
                         end
      {4'b0000,('b001 || 'b010 || 'b011)} : begin
                                              dir  = I2C_DIR_WRITE;
                                              size = 2;
                                            end
      {4'b0000,3'b100} : begin
                           dir  = I2C_DIR_READ;
                           size = 2;
                         end
      default          : `uvm_fatal(get_type_name(),"invalid idex or invalid command identified")
    endcase

while I declared logic and enum before case I got the following error :
Illegal declaration after the statement near line 12. Declarations must precede statements. Look for stray semicolons

can anyone tell me reason for this error?

thanks

2

In reply to lalithjithan:

Illegal declaration after the statement near line 12. Declarations must precede statements
This means you cannot declare variables after the assignment statement in a begin…end block;

Declare before you create sequence like below

task data_...... ()
    logic size;          
    enum{write,read} dir;
    req = i2c_sequence_item::type_id::create("req");