Strange behaviour when variable is re-declared in the extended class

SystemVerilog
1

Hi Experts,

I am observing a strange behavior when same variable is re-declared in an extended class.
Following is the code :


class parent;

rand int unsigned color;

constraint c1 { color inside {[1:10]};}

virtual function calc_crc();
   color = 10;
   this.randomize();
endfunction

endclass


class child extends parent;

rand int unsigned color;

constraint c2 { color inside {[50:100]};}

virtual function calc_crc();
   color = 70;
   this.randomize();
endfunction

endclass


module tb();
initial
begin
   parent p1, p2;
   child c1, c2;
   c1 = new();
   c1.calc_crc();
   p1 = c1;
   $cast(c2, p1);
   $display("c1.color = %d p1.color = %d c2.color = %d",c1.color, p1.color, c2.color);
end

Following is the output of the simulator :
c1.color = 69 p1.color = 10 c2.color = 69

Now, there is only a single object created in the entire flow which corresponds to child class.
How come p1.color is attaining a value 10?

2

In reply to abhi_inno:

This is Inheritance+Over-riding.

When you extend any class, the extended class inherits the parents members and methods. Because of which, when you create(new) an extended class, all the members/functions in Parent are also created along with the additional members/functions in the extended class.

So, in your example when child is created (new()), memory will be allocated to two color variables one for parent ‘color’ and one for child ‘color’. And when you try to access color from the respective handles the respective values are printed.

3

In reply to S.P.Rajkumar.V:
I recommend against using parent and child when referring to OOP inheritance. Parents create(construct) children and they are distinct objects from their parents. When you inherit property, that property becomes yours and all your property belongs to one object. Use base and extended.

The UVM uses terms parent and child to refer to relationships between objects when build a hierarchical tree/graph structure. The class uvm_component has a handle to its parent and handles to all its children so that you can traverse the hierarchical structure. This terminology is used in most programming languages and is independent of OOP.

4

In reply to dave_59:

I was just referring to the example (parent, child) from the first post and hence this mix-up of terminology. Hope I didn’t create confusion.

5

In reply to S.P.Rajkumar.V:
I was adding to your reply.

6

In reply to dave_59:

Hi All,

Thanks for your response.
I am seeing yet another result when constraint block name in child class is renamed as 'c1".
Following is the result:
c1.color = 65 p1.color = 1370007103 c2.color = 65

I am unable to get how p1.color is getting a random value?

Regards,
Abhishek

7

In reply to abhi_inno:

Because the original constraint is over-ridden and only one constraint (the one in class child) is honored when this.randomize() is called from calc_crc of class child.

Where-as in earlier case, both constraints were in place applicable for the respective color’s.

8

It is an extremely bad practice reusing the same variable identifier name in an extended class. You might as well give it a different name because that is how the compiler sees it anyways. It is not and override—it is hiding the original variable name from the extended class. The base variable still exists and all references to that variable exist as well prior to the extended class.

9

Thanks everyone for your valuable inputs.
Now I understand how multiple declarations are treated by the simulator.