Strange behavior for fileIO function

I am trying to create an ASCII file using fileIO functions in verilog.


module tb_writer;
  integer fio;
  logic [7:0] li;
  initial begin
    fio = $fopen("ascii_file.txt", "w");

    if (fio == 0) begin 
      $display("data_file handle was NULL"); 
      $finish;
    end
    
    for (li = 0; li<32; li=li+1)
      $fwrite( fio, "%c", li);

    $fclose(fio);
  end
endmodule

While viewing the output file in a hex editor, I found that integer value 10 is taking 2 bytes and at the end of the file there are 2 extra bytes.

00000000: 0001 0203 0405 0607 0809 0d0a 0b0c 0d0e …
00000010: 0f10 1112 1314 1516 1718 191a 1b1c 1d1e …
00000020: 1f0d 0a …

I am using Modeslim - INTEL FPGA STARTER EDITION 10.5c.

Regards

In reply to bhargavmr:

Those two bytes are carriage return/linefeed and might be added by the OS. Try using “wb” instead of “w” to open the file for binary writing.

Thanks for your time. Opening the file with “wb” did not make any difference. I tried printing all values from 0 to 255, only printing 10 is behaving strangely. The simulator is printing 16’h0d0a instead of 8’h0a. Because of this and the 2 extra bytes at the EOF, I am seeing 3 extra bytes in my file. Could this be a simulator issue?

In reply to bhargavmr:

Must be a tool or OS issue because it works for on Linux.