I am trying to create an ASCII file using fileIO functions in verilog.
module tb_writer;
integer fio;
logic [7:0] li;
initial begin
fio = $fopen("ascii_file.txt", "w");
if (fio == 0) begin
$display("data_file handle was NULL");
$finish;
end
for (li = 0; li<32; li=li+1)
$fwrite( fio, "%c", li);
$fclose(fio);
end
endmodule
While viewing the output file in a hex editor, I found that integer value 10 is taking 2 bytes and at the end of the file there are 2 extra bytes.
00000000: 0001 0203 0405 0607 0809 0d0a 0b0c 0d0e …
00000010: 0f10 1112 1314 1516 1718 191a 1b1c 1d1e …
00000020: 1f0d 0a …
I am using Modeslim - INTEL FPGA STARTER EDITION 10.5c.
Regards