Static vs Automatic

SystemVerilog
,
1 

class a;
  static int b;
  static task update(int c = 0);
    b = c;
    $display("The value of b is = %0d", b);
   endtask
endclass

module check();
  a a1;

  initial begin
    a1 = new();
    fork
      begin
        #3 a1.update(4);
      end
      begin
       #3 a1.update(5);
      end
    join
  end
endmodule

The output is:
The value of b is = 4
The value of b is = 5

Why the output is not 4,4 or 5,5 as I am using static task as well as static property?

2

In reply to mukul1996:

Why would you expect the output to be 4,4 or 5,5? You are calling update() with a new value, which is updating the internal static value of ‘b’.

You have a race condition, so you could potentially have 4,5 or 5,4 but I’m not sure why you would expect something different.

3

In reply to cgales:

Hi,
As “b” is declared as static, the memory for it would be allocated only one time at a fixed position.

So when at #3 we call update with different values, the last update which got executed should reflect the value.

4

In reply to mukul1996:

You are correct, in that the last update which got executed will be the final value.

However, when you call update, you also immediately call $display, so the value is updated with the argument that is passed in and then displayed. There is nothing blocking between the assignment and $display to allow any task switching.

A better example would decouple the update and display:


class a;
  static int b;
  
  static function void print();
    $display("At time %0d The value of b is = %0d", $time, b);
  endfunction
  
  static function void update(int c = 0);
    b = c;
    print();
  endfunction
endclass
 
module check();
  a a1;
 
  initial begin
    a1 = new();
    fork
      begin
        #3 a1.update(4); // Update @time 3
        #1 a1.print();   // Display @time 4
        #3 a1.print();   // Display @time 7
      end
      begin
        #5 a1.update(5); // Update @time 5
        #1 a1.print();   // Display @time 6
      end
    join
  end
endmodule
5

In reply to cgales:

Note the lifetimes of your tasks are still automatic. The static qualifier on a class method means the method can be called without constructing the class and may only access static class members. See The life of a SystemVerilog variable