Hi,
In our current SoC, the system clock runs at 24ns and the doubler clock appears only after a time gap of 20ns from the clk_reset_block output.
Since our assertions written are trying to check unknown values, and is sensitive to the doubler clock which only starts after 20ns , the assertion fails much earlier at 12ns also.
Is there a way that assertion check starts to get enabled only after 20ns of time as the clocks are not up?
In reply to rsguptaji:
from my SVA Handbook 4th Edition
Use of a system function to disable the checking of the assertion
The assertion controls (e.g., $asserton, $assertoff, see 4.1.4.1) can be used to disable all, or selected assertions for a specific period of time. For example:
initial begin // ch3/3.10/always_prop.sv
$assertoff(0); // if called without arguments,
// it affects the entire design (e.g., $assertoff; )
repeat(2) @ (posedge clk2); // tune as needed
// #10 // or some duration ..
$asserton(0);
end
// here is another example:
module my_control(); // ch4/4.2/assertion_control.sv
initial begin : disable_assertions_during_reset
$display ("%0t %m Disabling assertions during init..", $time);
$assertoff (0, top_tb.cpu_rtl_1);
@ (top_tb.reset_n === 1'b1);
$display ("%0t %m Enabling assertions after init..", $time);
$asserton (0, top_tb.cpu_rtl_1);
end endmodule : my_control
module top_tb;
logic clk =1’b0, reset_n = 1’b0;
bus_if b_if; // Instantiation of interface
cpu_rtl cpu_rtl_1(clk, reset_n, .*); // Instantiation of cpu module
my_control my_control_1(); // instantiation of assertion control
..
endmodule : top_tb
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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