$stable functionality

SystemVerilog
1

Hi,
Can $stable detect glitch between two consecutive clock cycle or not ?
Below is my code and assert check is not failing at 25ns although glitch comes in between 15ns & 25ns ?

module stable_assrt_ex;
logic a,clk=1'b0;

property stable_1;
 @ (posedge clk)
$stable(a);
endproperty

initial
begin
 forever clk = #5 ~clk;
end

initial
begin
		a = 0;
	#7;	a = 1; //7ns
	#10;	a = 1; //17ns
	#2;	a = 0; //19ns
	#2;	a = 1; //21ns
	#10;	$finish;
end

assert property(stable_1);
  
endmodule

Log Error Message :
“testbench.sv”, 27: stable_assrt_ex.unnamed$$_2: started at 5ns failed at 5ns
Offending ‘$stable(a)’
“testbench.sv”, 27: stable_assrt_ex.unnamed$$_2: started at 15ns failed at 15ns
Offending ‘$stable(a)’

2

In reply to andrew187:
An assertion samples values on each edge of the clock and does not see intermediate values between clocks. Perhaps you want to look at timing checks in section 31 of the LRM.

3

In reply to dave_59:

Thanks Dave :)