$stable with clock cycles in the antecendent

SystemVerilog
1 
$rose(a) && $stable(a)[*337] |-> first_match(##[0:1000] !b)

I want to check when a changes from 0>1 and stays stable for 337 cycles, then check b=0 within 1000 cycles.
My assertion does not trigger. Anything wrong with $stable usage?

2

In reply to abhi9891:

Your problem is && is a boolean operator that has higher precedence than the [*n] sequence repeat operator. So it is being treated as
(rose(a) && $stable(a)) [*337] which of course is never true.

You could replace && with the and sequence operator, but why not keep it simple by writing

a[*337] |-> ##[0:1000]!b;
3

In reply to dave_59:

In reply to abhi9891:
Your problem is && is a boolean operator that has higher precedence than the [*n] sequence repeat operator. So it is being treated as
(rose(a) && $stable(a)) [*337] which of course is never true.
You could replace && with the and sequence operator, but why not keep it simple by writing

a[*337] |-> ##[0:1000]!b;

Thanks Dave…
a[*337] should work…
I have used first_match since i have something else also in my assertion consequent:

first_match(##[0:1000] !b) ##1 c

I want to check b once only and then move on to c.

4

In reply to abhi9891:

In that case, you may want to do

$rose(a) ##0 a[*337] |-> first_match(##[0:1000] !b) ##1 c