Splitting unpacked array using streaming operators

SystemVerilog
,
1

Hi everyone!
I try to split each element of array and write result into two arrays, like this:

module test();
  
  logic [31:0] data[] = new[5]({32'hAAAABBBB, 32'hCCCCDDDD, 32'hEEEEFFFF, 32'h00001111, 32'h22223333});
  logic [15:0] re[];
  logic [15:0] im[];
  
  initial begin
    
    {>>{im, re}} = data;
    
    $display("im = %p", im);
    $display("re = %p", re);
    
  end
  
endmodule

but result is:
im = '{'haaaa, 'hbbbb, 'hcccc, 'hdddd, 'heeee, 'hffff, 'h0, 'h1111, 'h2222, 'h3333}
re = '{}

how can i get this result:
im = '{'haaaa, 'hcccc, 'heeee, 'h0, 'h2222}
re = '{'hbbbb, 'hdddd, 'hffff, 'h1111, 'h3333}?

2

In reply to Pavel:
Something like:

    {>>{im with [data.size/2], re}} = data;

See 11.4.14.4 Streaming dynamically sized data in the 1800-2017 LRM

3

In reply to dave_59:

Hi! Thanks for response !

{>>{im with [0 : data.size-1], re}} = data;

This expression splits data array like this:

im = '{'haaaa, 'hbbbb, 'hcccc, 'hdddd, 'heeee}
re = '{'hffff, 'h0, 'h1111, 'h2222, 'h3333}

But this is not what I wanted.

4

In reply to Pavel:

OK, I didn’t look at your stream close enough. You want to split the upper and lower parts into each array. For that you will need a foreach loop.

module test();
 
  logic [31:0] data[] = {32'hAAAABBBB, 32'hCCCCDDDD, 32'hEEEEFFFF, 32'h00001111, 32'h22223333};
  logic [15:0] re[];
  logic [15:0] im[];
 
  initial begin
    re = new[data.size()];
    im = new[data.size()];
    foreach(data[e]) {im[e],re[e]} = data[e];
    $displayh("im = %p", im);
    $displayh("re = %p", re);
 
  end
 
endmodule
5

In reply to dave_59:

OK! Thanks! I thought it could be done without a loop.