Specifying Time Unit , Precision and $timeformat for Classes

SystemVerilog
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1

Hi All ,

I am trying following code :: edaplayground

The Output I observe is as follows :

(1) For +define+CD ::

 **Time scale of (tb) is  10ps /  10fs
 Time scale of (my_pkg.test.main_phase) is  10ns /  100ps
 Time scale of (my_pkg.seq.body) is  10ns /  100ps**

(2) For No +define ::

 **Time scale of (tb) is  10ns /  100ps
 Time scale of (my_pkg.test.main_phase) is  1ps /  1fs 
 Time scale of (my_pkg.seq.body) is  1ps /  1fs**

My understanding is as follows ::

(1) For +define+CD :: Due to include "my_pkg.sv" in top_tb , the latter compiler directive i.e timescale 10ps / 10fs is used for the module

                      However  for  both  the  class  ,  the  time  unit  is  10ns  and  time  precision  is  100ps  
                      i.e  the  former  compiler  directive  i.e  `timescale 10ns / 100ps  is  used .

                      **[Q1]  How  is  time  unit  and  time  precision  determined  for  both  classes  ?**

(2) For No +define :: The output is as per expectations i.e the module uses the compiler directive declared in it
whereas the classes use the timeunit and timeprecision declared in package .

[Q2] How do I specify $timeformat for uniform output via %t for all classes included within the same package ?

2

In reply to MICRO_91:

The order in which compiler directives are compiled always matters. The timescale directive only affects modules and packages defined *after* it appears within the same compilation unit. Since <span style="font-family:'courier'"> \include “my_pkg.sv” appears right after the timescale in the testbench.sv file, the first <span style="font-family:'courier'"> \timescale applies to the package. But since the
`timescale 10ps / 10fsappears after the
package my_pkg; declaration.

The
timeunit declaration was intended to replace the
`timescale directive so that compilation order was no longer a problem.