Specify Block

SystemVerilog
,
1

Hi,

I am writing a code, in which clock period is depend on one signal like CK_BYPASS,
if CK_BYPASS is one clock frequency must be 20Mh
if CK_BYPASS is zero clock frequency must be 40Mh
in between simulation CK_BYPASS can change
how to specify the clock period depend on CK_BYPASS?

if(CK_BYPASS)
$period (posedge CK, MEM_PERIOD_CKB1, NOT_CK_MINPRD);
else
$period (posedge CK, MEM_PERIOD_CKB0, NOT_CK_MINPRD);

above code is giving error.
please help me on this.

2

In reply to LOHIHTHA DM:

$period (posedge CK &&&  CK_BYPASS, MEM_PERIOD_CKB1, NOT_CK_MINPRD);
$period (posedge CK &&& !CK_BYPASS, MEM_PERIOD_CKB0, NOT_CK_MINPRD);

This is explained in section 31.7 Enabling timing checks with conditioned events of the 1800-2017 LRM

3

In reply to dave_59:

hi Dave sir,
Thank you for the information, it helps a lot.

4

In reply to LOHIHTHA DM:

hi dave sir,
can i write multiple conditions to enable the timing checks
clock period may change if let say 100ns then both write and read is success
if 50ns only read is success but write cannot be success.

$period (posedge CK &&& CK_BYPASS &&& WEN, MEM_PERIOD_CKB1_READ, NOT_CK_MINPRD_READ);
$period (posedge CK &&& CK_BYPASS &&& ~WEN, MEM_PERIOD_CKB1_WRITE, NOT_CK_MINPRD_WRITE);

i am getting the below error like expecting a comma.

5

In reply to LOHIHTHA DM:

No, the syntax only allows one ‘&&&’