Soft constraints vs Hard constraints

SystemVerilog
,
1

There is a config object with random variables that are constrained by soft and hard constraints. Two instances of this config object are created. Variables in one instance take soft constraint value but variables in the second instance do not. These values are not constrained anywhere else other than this config object.

class config_object;
rand int unsigned var1, var2;
constraint c_default {
soft var1 == 10;
soft var2 == 15;
}
constraint c_var1 {
var1 inside {9,10,11,12};
}
constrain c_var2 {
var2 inside {14,15,16,17};
}
endclass
Test results:
config_object[0].var1 = 10
config_object[0].var2 = 15
config_object[1].var1 = 12
config_object[1].var2 = 16

Any reason why the variables for both instances don’t take the soft constraint values?

2

In reply to Sharandiva:

You need to show a complete example. I’m not seeing your problem with my code.

3

In reply to dave_59:

Here is the complete code:
There are 2 levels of hierarchy.

class config_object;
  rand int unsigned var1, var2;
  rand enable;
  constraint c_default {
    soft var1 == 10;
    soft var2 == 15;  
  }
  constraint c_var1 {
    var1 inside {9,10,11,12};
  }
  constraint c_var2 {
    var2 inside {14,15,16,17}; 
  }
endclass

class test_config;
  rand int unsigned var;
  rand config_object cfg[2];

  constraint c_t_var1 {
    solve cfg[0].enable before solve cfg[0].var1;
    solve cfg[0].var1 before solve var1
    solve cfg[1].var1 before solve var1
    if ( cfg[0].enable)
      var1 == cfg[0].var1;
    else
      var1 == cfg[1].var1;
  }
  //similar constraint for var2
  
endclass

In the post_randomize function of the config_object, when I print the variables:

config_object[0].enable = 0;
config_object[0].var1 = 10
config_object[0].var2 = 15
config_object[1].enable = 1;
config_object[1].var1 = 12
config_object[1].var2 = 16
test_config.var1 = 12;
test_config.var2 = 16;

Thanks Dave!

4

In reply to Sharandiva:
This is much more complicated than your original post. How about providing a complete self-contained run-able testcase so there are no other misunderstandings.

5

In reply to Sharandiva:

Just to add, nothing in your second example can result in ignoring the soft constraints. Since test_config.var1 and test_config.var2 depend on cfg[0/1].var1 and cfg[0/1].var2, if you have additional constraints on test_config.var1/var2 that would contradict with the soft constraints, this could result in the behavior you are seeing. For example:


if ( cfg[0].enable)
      var1 == cfg[0].var1;
      var1 != cfg[1].var1; //contradicts soft constraints
    else {
      var1 == cfg[1].var1;
      var1 != cfg[0].var1; //contradicts soft constraints
    }

So a full example will clear any remaining confusion.

6

In reply to Sharandiva:

Regarding this piece of the code where is var1 declared in the class test_config:

solve cfg[0].var1 before solve var1
solve cfg[1].var1 before solve var1

is there any missing part

Thanks,
Nikhil

7

ard constraints are those which we definitely want to be true. These might relate to the sucessful assembly of a mechanim. Soft constraint are those we would like to be true - but not at the expense of the others. These might say that a mechanism must follow a given path. There is not point in trying to match every point exactly if this can only be done by breaking the assembly of the links.