Soft constraint not overridden by hard constraint

SystemVerilog
1

I have a class , where data is a 4 bit member .

class verify_soft_constraint ;

rand bit [0:3] data ;

constraint c_data {

            soft data >4; 
            data >20;

               };

endclass

Randomize is being called as below :

module test_soft_constraint ();

verify_soft_constraint test_verify_soft_constraint =new ();

initial begin

for(int i=0 ; i<5 ;i++)begin
test_verify_soft_constraint.randomize() ;
$display(“value of data =%0d i=%0d” , test_verify_soft_constraint.data , i);
end

end
endmodule

When I run the above code , I’m getting constraint inconsistency failure .I expected the hard constraint to override the soft constraint and randomise .I’m not seeing this behaviour .Can any of you please let me know the reason behind this behaviour ?

Regards

2

In reply to ra_su:

The error is with the constraint ::

 data > 20 ;

Since data is 4-bits it has max value of 4’d15 .
So it can NEVER be Constrained to be greater than 20

3

In reply to ABD_91:

Thanks .Got it