Soft constraint with if-else

SystemVerilog
,
1

How to make the following constraint a soft one?

 constraint x_has_read_c {
    solve fabric_id before x_has_read;
    if (fabric_id inside {G0, G1, G2,G3}) {
      x_has_read == 1;
    }
    else
    {
      x_has_read == 0;
    }
  };
2

In reply to 1978bubun:

What happen if you use:


 constraint x_has_read_c {
    solve fabric_id before x_has_read;
    if (fabric_id inside {G0, G1, G2,G3}) {
      soft x_has_read == 1;
    }
    else
    {
      soft x_has_read == 0;
    }
  };