Hi,
I am getting compilation error for the below constraint code with Questasim 2022.3, the code is fine with Cadence. Is there any issue with the code?. If so how can i restructure it for Questa?
soft (channel == -1) && (p_info_type == INIT) -> {
released_hdr_cr_p dist{ 0 := 10, 1 := 10, [5:15] := 20, MAX_HDR_CR_P := 50, [16:50] := 10};
released_data_cr_p dist{ 0 := 10, 14:= 10, [15:45]:= 20, MAX_DATA_CR_P:= 50, [16:50] := 10};
}
** Error: (vlog-13069) ** while parsing file included at …/…/…/tbcs/pcie_sw_core/sv/lw_102_pcie_sc_pkg.sv(37)
** at …/…/…/tbcs/pcie_sw_core/sv/lw_102_pcie_sc_cr_pkt.sv(146): near “dist”: syntax error, unexpected “SystemVerilog keyword ‘dist’”, expecting ‘,’ or ‘}’.
Regards
Sujesh