SMART REGRESSION

SystemVerilog
1

Hi,

In my regression , i run tests multiple times to get different random values. For example i have a random variable with 4 possible values. If i run the test for 4 times ( Even 8 times), there is no possibility that all 4 values get covered.

I am trying to do a smart regression, where with four runs i should be able to cover all values. Is there any way to do this ?

I tried the following

  1. Include a text file and on each run add a constraint that it should not be covered next time ( example :constraint c_n { x!= 2;} )
    With this approach we need to compile the bench again and when tests are running parallel, accessing same file is difficult.

  2. Include a ignore_list queue.
    bit [2:0] x_ignore_lsit[$];
    constraint x_c { !(x inside {x_ignore_lsit}); }
    Write covered values in to a file.
    Update the ignore list by reading from the file.

    With this we don’t need to compile again but accessing the file in regression is difficult.

  3. Run a dummy regression initially. Make sure you randomise test variables in build phase and kill the test case in run phase. And analyse the coverage ( add embedded coverage in the class). Once we get the best seeds we run the actual regression with specific seeds.

Have to find a way to do this....
2

In reply to krishna4589:

This is difficult to achieve within the limits of SystemVerilog. To achieve this easily, you should use Questa inFact.

3

In reply to krishna4589:

Since you know the values you want to use, create a new plusarg on the cmdline where you set the value you want to use. Then each time your regression script invokes a sim, set a different value.

You could use a Python script to generate a list that’s a cross of the values you want to test vs. the tests that you have. That way you can also control so you don’t run with a {value, test} combination that makes no sense.

InFact will do what you want as well - but that involves paying money and learning a new tool.