Size casting of value with X at MSB

SystemVerilog
1

In case there is an X at the MSB and the value is casted to a larger bit width,
what is the result of the cast?


logic [3:0] i=4’sbx000;
logic [7:0] d;
d = 8’(i);  // value of d ?

Which rule of the LRM does handle this topic?

Thanks and best regards,
Thomas

2

In reply to Thomas Kruse:

You declared i as an unsigned variable. The fact that you used a signed literal or any signed expression in the initialization is lost. When changing the size, the LRM says

The signedness shall pass through unchanged, i.e., the signedness of the result shall be the self-determined signedness of the expression inside the cast.

So 8’(i) 0 extends an unsigned expression.

3

In reply to dave_59:

Thanks, Dave, for your quick answer!

Does it means that in


logic signed [3:0] si = 4’sbx000;
logic signed [7:0] sd;
sd = 8’(si);

sd would be 8’bxxxxx000 ?

Thanks again and best regards,
Thomas

4

In reply to Thomas Kruse:

Correct. You can try all these little examples on www.edaplayground.com.