can anyone write me a simple testbench with following signals with interface , monitor , generator , etc…find it below…and if you can…please provide comments wherever this code can get complicated for a beginner…a simple testbench with following classes will be very helpful
Write following classes for a System Verilog TestBench :
- DUT
- Interface
- Top
- Environment
- Packet
- Driver
- Receiver
- Testcase
○ Interface has following signals :
clk : clock
rst : asynchronous reset
addr : address for read/write data
data_out : data to be written to DUT
data_in : data read from DUT
chip_sel : Chip select.
It must be high .
wr_rd : Write / Read select signal.
If wr_rd=0 => Write data_out to DUT register at addr.
If wr_rd=1 => Read data_in data from DUT register at addr.
…
i need a DUT something like this…as a array which stores a data…find it below
may be , my DUT will have some errors … do accordingly …with ur expertice , which i need the most right now
…this answer will decide whether i’ll get my job or not…soooo…need help
module memory(
input clk;
input rst;
input [7:0]addr; //width
// input [7:0]data;
input wr_rd;
input [7:0] data_in;
output [7:0] data_out;
);
reg [7:0] data_out ;
reg [7:0] mem [256]; // array length
always @(posedge rst)
for(int i=0;i<8;i++)
mem[i]=8’hFF;
if (chip_sel==1)
begin
always @(posedge clk)
if (wr_rd==0) mem[addr] <= data_in;
always @(posedge clk)
if (wr_rd==1) data_out <= mem[addr];
end
endmodule