Simple Problem of Systemverilog

[Holzapfel]

Hallo everyone,

Im very new to sv and I have a quite simple question.

I have 3 module now, lets say there a module_1,module_2 and module_3.
Module_1(input a_1,output a_1);
module_2(input a_2,output a_2);
module_3(input a_3,output a_3);

Now I want to instance module_2 and module_3 in module_1, and conncet output a_2 to input a_3, so I create a signal “signal_transport” in module_1:
module_1(input a_1,output a_1);
module_2 instance_module_2(.input a_2(input a_1),.output a_2(signal_transport));
module_2 instance_module_3(.input a_3(signal_transport),.output a_3(output a_3));

But after I run simulation in modelsim, I get error like “signal_transport is driven via a port connection, is multiply driven”. How can I solve thsi probelm?
By the way,since all the inputs and outputs are type logic, so I use signal_transport as logic too.

Thanks a lot for help!

[ben2]

In reply to Holzapfel:

1. This forum does not address tools. If you want to refer to a tool’s error message, just say something like My simulator reports that …

The following works OK in my simulator,

module m_2(input logic in2, output logic out2); endmodule
module m_3(input logic in3, output logic out3); endmodule
module m_1(input logic in1, output logic out1); 
    logic s; 
    m_2 m2_a(.in2(in1),.out2(s));
    m_3 m3_a(.in3(s),.out3(out1));

endmodule  

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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• SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
• Component Design by Example ", 2001 ISBN 0-9705394-0-1
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• VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

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