What is the significance of flower braces for $random? Could anyone explain the concept involved.
add=$random%10; //–>Generates signed numbers (2,-3,6,-1)
add={$random}%10; //–>Generates unsigned numbers (1,5,2,6)
Have attached eda link for reference.
In reply to Chandra Shekar N:
The braces {} represent the concatenation operator, which always returns an unsigned result. In this example, there is only one operand in the concatenation. So the only effect it has is casting the signed result of $random operand to unsigned. (btw, you have the example generated output swapped).
This is an obscure way of coding. It would be much more advisable to write
add = $unsigned($random) % 10;
In SystemVerilog, $urandom should always be used instead of $random. Besides returning a 32-bit unsigned value, it also has much better seeding and stability. See section 18.14 Random stability in the IEEE 1800-2017 SystemVerilog LRM.
In reply to dave_59:
Hi Dave , I tried this code but after concatenation also it is returning signed value.
Have attached eda link for reference.
In reply to Parag_N_Sonawane:
The concatenation expression you wrote is illegal. You are not allowed to use numeric literals without an explicit size as operands to a concatenation. All the other tools on EDAplayground produce an error or warning.
The reason for this restriction is people forget that an unsized literal is implicitly 32 bits. So {5,-1} would actually be equivalent to the literal 64’h0000_0005_FFFF_FFFF, if it were allowed. When you assign that to the 32-bit signed integer add, it gets truncated to 32’hFFFF_FFFF, which is -1 when displayed as a signed value.