Is there any problem on using signed variables in constraint?
In reply to bachan21:
More important is understanding how signed arithmetic works in Verilog expressions
https://2020.dvcon-virtual.org/sites/dvcon20/files/2020-05/12_1_P.pdf
Is there any problem on using signed variables in constraint?
In reply to bachan21:
More important is understanding how signed arithmetic works in Verilog expressions
https://2020.dvcon-virtual.org/sites/dvcon20/files/2020-05/12_1_P.pdf