Signed Expressions and Expression bit lengths

SystemVerilog
1

Hi,

Can any help on these two questions? The example is taken from 11.6.3 and 11.7 of LRM.



In the below example, 
Question 1: I would like to know why is c = {a**b} size is 4 bits.

logic [3:0] a;
logic [5:0] b;
logic [15:0] c;
initial begin
a = 4'hF;
b = 6'hA;
$display("a*b=%h", a*b); // expression size is self-determined
c = {a**b}; // expression a**b is self-determined
// due to concatenation operator {}
$display("a**b=%h", c);
c = a**b; // expression size is determined by c
$display("c=%h", c);
end

Question 2:  In the below example, -4'sd4 is equal to 1100 and $unsigned does zero extension and the output is 0000_1100. Is my understanding correct?


logic [7:0] regA, regB;
regB = $unsigned(-4'sd4); // regB = 8'b00001100
2

In reply to rag123:

Q1: because each operand of a concatenation has a self-determined width. The self-determined width of ab** is the width of a. But the 4-bit result of the concatenation will be zero-extended to 16-bits and then assigned to c.

Q2: You can test this yourself.