Signed Arithmetic Query

SystemVerilog
,
1

My code has the following declarations:

 
input wire signed [11:0]  vec;
var real            lcl;

The following is the assign code:


assign              lcl   = (vec * 0.2)/2047;

When vec = 'h800, the lcl has the value -0.2

Can anyone explain how is the signed arithmetic coming into the picture?

2

In reply to prashantg:

When vec gets converted from in integral to real, it becomes -2048.0