Signed and unsigned mix operations in SV

SystemVerilog
1

Hi,

What would be the result if we do some operations on mixed signed and unsigned variables?

For example:

  1. I have an signed and unsigned vars and i am assigning a unsigned to a signed variable. what would happen in this case?
    bit [31:0] a = 32’h10000001;
    int b;
    b = a;
    Here will b become a negative value?

  2. I have a signed and unsigned numbers imagine
    int a = 32’h1000_0001;
    bit [31:0] b = 32’h0000_0001;

    What happens if I do an add and store it an signed and unsigned?
    int res_s;
    bit [31:0] res_uns;

    res_s = a+b;
    res_uns = a+b;

    what values will res_* will get?

Thanks.

2

In reply to jaswanth_b:

The signedness of an expression only affects certain operations like extension and the relational operator. It has no effect on the arithmetic operators, or how assignments work when there is no extensions needed.

If you have

bit [31:0] a = 32'h80000001;
int b;
b = a;

The 32-bit pattern in a gets assigned to b. That pattern represents a negative number in b because the MSB is set.