In reply to dave_59:
Thanks Dave that helped :) one last question, Can we use the same ARG to define multiple bits? I tried this and it shows error. but when i tried with a separate define it worked.
// Code your testbench here
// or browse Examples
`define master1(ARG1,ARG2) \
ARG2 = m_mst_``ARG1;
`define master2(ARG) \
bit m_mst_``ARG \
bit b_mst_``ARG ;
module test;
bit var_1;
`master2(3)
`
//`master2(3)
initial begin
// m_mst_``ARG1 = 1;
`master1(3,var_1)
end
endmodule
