Signal delay by X clock cycles in System Verilog

Question

Hello everyone,

I am new to Verilog.

I'd like to delay a signal by 5 clock cycles. Right now I am doing this by just copying a signal 5 times, but isn't there a more comfortable way?

fs_shift1_model_o <= fs_model_o; //Delay for 5 clock cycles
fs_shift2_model_o <= fs_shift1_model_o; //to compare the frame syncs
fs_shift3_model_o <= fs_shift2_model_o; //of the DUT & the model
fs_shift4_model_o <= fs_shift3_model_o; //1 copy = 1 cycle
fs_shift5_model_o <= fs_shift4_model_o;

I found that there is a function named buf(x,x) (out,in) but there's a limit, I think 1 cycle.

Thanks in advance,
René

Answer 1

Solution

dave_59

Forum Moderator

10890 posts

January 26, 2016 at 9:05 am

In reply to RenéPi:

fs_shift5_model_o <= repeat (5) @(posedge clk) fs_model_o;

buf() is not a function, it is a gate-level primitive that instantiates a process.

— Dave Rich, Verification Architect, Siemens EDA

Answer 2

RenéPi

Forum Access

10 posts

January 26, 2016 at 11:52 pm

In reply to dave_59:

thanks a lot for your answer. really appreciate your support! This works perfect, but somehow I just had to use:

fs_shift_model_o <= repeat(4) @(posedge clk) fs_model_o;

to give me the expected result! This is way more comfortable than making several copies for a delay!

Many thank and have a nice day :)

Answer 3

Faisal Saeed Awan

Full Access

2 posts

December 08, 2022 at 10:04 am

Hope you are doing well,I have a question that if we want to make synthesizable design for N cycle delay of 32 bit signal at output then what will be the verilog code for this. I will really appreciate your answer

Thank you

Answer 4

dave_59

Forum Moderator

10890 posts

December 08, 2022 at 12:15 pm

In reply to Faisal Saeed Awan:

You can use a fifo for this.

typedef logic [31:0] uint_t;
parameter N = 5;
wire uint_t in, out;
 
var uint_t fifo[N];
 
always @(posedge clk)
     fifo[N-1] <= in;
 
for(genvar i=0;i<N-1;i++)
  always @(posedge clk)
     fifo[i] <= fifo[i+1];
 
assign out = fifo[0];

If N is not a parameter, you will have to define a maximum number of cycle delays for the size of the fifo, and then add a mux to select where the input to each stage of the fifo comes from.

typedef logic [31:0] uint_t;
parameter Max= 5;
int N;
wire uint_t in, out;
var uint_t fifo[N];
 
for(genvar i=0;i<Max;i++)
  always @(posedge clk)
     fifo[i] <= (i==(N-1))? in : fifo[i+1];
 
assign out = fifo[0];

— Dave Rich, Verification Architect, Siemens EDA

Answer 5

Faisal Saeed Awan

Full Access

2 posts

December 08, 2022 at 9:35 pm

Thank you Dave, the design code working perfectly :)

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