I am new to Verilog.
I'd like to delay a signal by 5 clock cycles. Right now I am doing this by just copying a signal 5 times, but isn't there a more comfortable way?
fs_shift1_model_o <= fs_model_o; //Delay for 5 clock cycles
fs_shift2_model_o <= fs_shift1_model_o; //to compare the frame syncs
fs_shift3_model_o <= fs_shift2_model_o; //of the DUT & the model
fs_shift4_model_o <= fs_shift3_model_o; //1 copy = 1 cycle
fs_shift5_model_o <= fs_shift4_model_o;
I found that there is a function named buf(x,x) (out,in) but there's a limit, I think 1 cycle.
Thanks in advance,