Sig1 should remain low after first pulse of sig1 till Sig2 is asserted

SystemVerilog
,
1

Hi,

I need to write an assertion where the SIG1 is high for 1 pulse and after that remains low till SIG2 is asserted.

SIG1 !SIG1 … …!SIG1… SIG2&!SIG1 … then SIG1 can go high.
1 0 … 1 & 0 …

I get a failure with below property.

assert_check: assert property (rose(SIG1)) |-> ((!SIG1[*1:]) intersect (SIG2));

Thanks
Irshad

2

In reply to Mohammed Irshad:
Need the goto on sig2

 
assert_check: assert property ($rose(SIG1)) |-> 
     ((!SIG1[*1:$]) intersect (SIG2)[->1] );

Ben systemverilog.us

3

In reply to ben@SystemVerilog.us:

Thank you, the Goto operator solved the issue.

-Irshad

4

In reply to ben@SystemVerilog.us:

Hi Ben,

How about this approach? Avoiding [1:$] can improve the simulation performance.

$rose(SIG1) |=> !SIG1 throughout SIG2[->1];

Regards,
Manju

5

In reply to mbhat:

Many ways to skin a cat.
Looks OK too,maybe even more concise, thanks!
Ben systemverilog.us