Should we randomize validation bits "valid_bit" or not?

SystemVerilog
,
1

iam beginner at sv test bench enviroment blocks
here in this piece of code the driver class pass the data to the interface through the virtual interface
my first question , when we need to verify a design should we randomize the valid bit “as it may be a test-case to cover”
my second question , the values of the input signals should be initialized in the generator class or it can be initialized in the driver as follows

driver piece of code :


  task drive;
      transaction trans;
      gen2driv.get(trans);
      @(posedge vif.clk);
      vif.valid <= 1;
      vif.a     <= trans.a;
      vif.b     <= trans.b;
      @(posedge vif.clk);
      vif.valid <= 0;
      trans.c   <= vif.c;
      @(posedge vif.clk);
      trans.display("[ Driver ]");
      no_transactions++;
    end
  endtask
2

In reply to le_NOIRE2000:

Typically one separates data associated with transaction from the protocol in the interface used to drive the transaction. All data in the transaction should be initialized by the generator. This makes it easier to maintain changes to your protocol as well as making your generators and drivers more re-usable in other parts of the same design, or other designs.

I assume your “valid” bit is part of the protocol. Dealing with errors in the protocol probably requires using a different driver task. In an Object-Oriented testbench, you would override the driver class with an Error_driver for a particular test.

These are general guidelines that fit most situations.

3

In reply to dave_59:

thanks dave.
do u recommend any book that provide guidelines that will help to improve my verification skills ?

4

In reply to le_NOIRE2000:

Verification Academy:
SystemVerilog OOP for UVM Verification
Books:
SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
Introduction to SystemVerilog