Shift Register Implementation

SystemVerilog
1

Hi all!
While implementing simple shift register:

reg [3:0] Input_Delay;
  
always @(posedge clock)
  begin
    // Create a delayed version of signal Input
    Input_Delay    <= Input_Delay << 1;
    Input_Delay[0] <= Input;
  end

I have noticed that If I change the lines order:

   Input_Delay[0] <= Input;
   Input_Delay    <= Input_Delay << 1;

it does not work as expected, why?

Thanks!

2

In reply to mago1991:

I believe you want to implement synthesizable logic.

The above code in any order will cause multiple drivers on Input_Delay[0].
Best way of writing is:

   Input_Delay <= {Input_Delay[3:1], Input};
3

In reply to yourcheers:

You can have multiple assignments to the same variable in the same always block, but the last assignment wins.

When you put the assignment to Input_Delay[0] first, it gets overwritten by the next assignment which is always 0.

4

In reply to dave_59:

but then how the following works:

	always_ff @(posedge sys_clk) begin
		if (sys_rst)begin
			a <= 1'b0;
			b <= 1'b1;
		end else begin
			a<=b;
			b<=a;
		end
	end

here, a and b will switch every clock cycle… so it does not seems like one overwrite the other or I don`t understand the meaning of “it gets overwritten by the next assignment”

5

In reply to mago1991:

In your always_ff block, there is only one assignment to a and one assignment to b in each clock cycle.

In the original example, there are two assignments to Input_Delay[0] in each clock cycle, but only one assignment to Input_Delay[3:1] in each clock cycle.