Sets of cover bins for mask bits

SystemVerilog
,
1

Hi,

First question:

My requirement is I wanted to generate cover bins for a field which is having 32 bits of width.



bit [32:0] masks;

Valid values are,
'h0000_0000
'h0000_000f
'h0000_00f0
'h0000_00ff
'h0000_0f00
'h0000_0f0f
'h0000_0ff0
.
.
.
'hffff_ffff

So as per above valid fields, I have to explicitly code bin for each mask. And actually I have taken 32-bits width for explaining this example. My actual width of masks is 64 bits.

I surfed many forums/other questions, not found related same query.

Second question is,

Is it possible to divide field width within a coverpoint?



bit [32:0] masks;

covergroup cg_masks;

  cp_masks : coverpoint masks {

    bins maskLSB = // Here I wanted to sample masks[15:0]
    bins maskMSB = // Here                    masks[31:16]    

  }

endgroup : cgmask
2

In reply to electron:

For your first question, you can put your bin values into an array, and use the array in the bin specification. See Verification Horizons - Siemens Software

For your second question, the coverpoint expression defines the value to be sampled. You could write

cp_masksLSB : coverpoint masks[15:0] {
    bins maskLSB = // Here I wanted to sample masks[15:0];
  }
 cp_masksMSB : coverpoint masks[31:16] {
    bins maskMSB = // Here                    masks[31:16];
  }

If that doesn’t work for you, take a look at the wildcard bin specification.

3

In reply to dave_59:

For my first que,
Got an Idea, Thank you.

For my second que,
I already coded what you have mentioned in above comment, However I am quite curious to know why it is not possible to sample/access partial field inside coverpoint (like with different bins)?

I even tried below wildcard bins


bins masksMSB = {['h0000_???? : 'hffff_????]};

I didn’t run and check but is it same what you wanted to convey me in your last statement?

4

In reply to electron:
You can’t use a wildcard in range of values, but you can do

wildcard bins masksMSB = {'h0000_???? , 'hffff_????};
5

In reply to dave_59:

I tried that array assignment to cover bins, it is giving below error

Feature is not yet supported: expression other than coverpoint label as coverpoint bin value.

Actually my covergroups are in class entity, may be that’s why.

6

In reply to electron:
As I mentioned in my blog post, this is a newer feature of SystemVerilog 1800-2012 and works in Questa. Take it up with your vendor.

7

Conclusion on my both questions based on Dave’s reply,

For question one,
We can put bin values in array, but my current vcs tool is not supporting. So I am going ahead with explicit bin assignment.

For question two,
Partial field assignment is not possible in single coverpoint for different bins. Kept separate coverpoints implementation for MSB and LSB. Wildcard is not helping in my case.