Set all zero in the constraint

SystemVerilog
,
1

if I have a transaction which has lots of bit variables as shown below. How to create a constraint that make sure all of them are 0


class my_trans extends uvm_sequence_item;

    function new(string name = "my_trans");
        super.new(name);
    endfunction : new

    rand bit [1:0] a1;
    rand bit a2;
    rand bit [2:0] a3;
    rand bit [1:0] a4;    
    rand bit [4:0] a5;
    rand bit a6;    
    rand bit [4:0] a7;
    rand bit a8;
    rand bit [11:0] a9;
...

endclass
2

In reply to zz8318:

When you first construct the class, all variables will be 0, the default for the bit type.

3

In reply to zz8318:

if I have a transaction which has lots of bit variables as shown below. How to create a constraint that make sure all of them are 0


class my_trans extends uvm_sequence_item;
function new(string name = "my_trans");
super.new(name);
endfunction : new
rand bit [1:0] a1;
rand bit a2;
rand bit [2:0] a3;
rand bit [1:0] a4;    
rand bit [4:0] a5;
rand bit a6;    
rand bit [4:0] a7;
rand bit a8;
rand bit [11:0] a9;
...
endclass

Hi,
You can write a constraint in the same transaction class as below:
constraint all_zeros {
a1 == '0;
a2 == '0;
a3 == '0;
…and so on…
a9 == '0;
}

This constraint will generate all zeros pattern.

Regards,
Pradeep Chandra.

4

In reply to avpchandra:

I think you did not get what Dave said. The default value for bit type is always zero. They do not need to be initialized. And if you want them to be zero always then just remove the “rand” specifier and they will always be zero :)

5

In reply to dave_59:

Thanks All.