Sequence transition bins vs array of transition bins

SystemVerilog
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1

bins sa = (4 => 5 => 6), ([7:9],10=>11,12);
bins sb = (4=> 5 => 6), ([7:9],10=>11,12);

Can someone explain difference?

2

In reply to mi:

The LRM explains how the bins get constructed for this example. Bins sa/sb defines 9 possible transitions. sa will have one bin for hitting any one of those transitions, and sb creates 9 bins for each transition.

3

In reply to dave_59:

Thanks Dave.

What is mean by each transaction please elaborate it (example please if possible for both)

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In reply to mi:

The LRM section where you got these examples from elaborates the 9 possible transitions.