The error message is because you are using the wrong sequence ANDing operator.
- && is a logical AND.
- and is a sequence AND
thus (a ##1 b) and (c ##[1:3] d)
In “sequence A(signal, event);”, event is a type and not an argument.
You can do sequence A(signal, event e);
Your property definition is very unusual as you are using the clocking event as the leading clocking event (OK, should be like this), BUT then in “B(bus3[win], bus2[win])” you use a sequence as a clocking event. This is not how things are done typically.
Sequences can be used as clocking event, but they are rarely used as such. Below is code that simulates, though i am not much of a proponent of using sequences as clocking events; I never do that, but I address it in my SVA book.
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, a, b, c;
default clocking @(posedge clk);
endclocking
initial forever #10 clk=!clk;
sequence q1;
@(posedge clk) a ##1 b;
endsequence
always begin
@(q1) if(c!=1'b1) $display("%t error, c!=1", $realtime);
end
ap_q1c: assert property(@(q1) c); // Unusal usage of sequence as clocking event
// typical usage: @(posedge clk) q1 ##0 c; //
// Better usage: @(posedge clk) q1 |-> c; //
initial begin
repeat(200) begin
@(posedge clk); #2;
if (!randomize(a, b, c) with
{ a dist {1'b1:=1, 1'b0:=3};
b dist {1'b1:=1, 1'b0:=2};
c dist {1'b1:=1, 1'b0:=1};
}) `uvm_error("MYERR", "This is a randomize error")
end
$stop;
end
endmodule