In reply to ssureshgverifier@gmail.com:
From 1800'2017 16.12.11 Always property
//Implicit form:
implicit_always: assert property(p);
//Explicit form:
initial explicit_always: assert property(always p);
/*This is not shown as a practical example, but only for illustration of the meaning of always. Examples:*/
initial a1: assume property( @(posedge clk) reset[*5] #=# always !reset);
/*The assertion a1 says that reset shall be true for the first 5 clock ticks and then remain 0 for the rest of the computation. */
Thus, in the above solution you would need the
initial, Otherwise, you have a new attempt at every clock edge. You might argue that since there is no rose of pulse, the new attempts are vacuous, you are correct. However, why putting more stress on the simulator. In addition, it does not read correctly since the
always takes care of future clocks; it is the the explicit form of the
always. initial ap_pulse: assert property(@(posedge clk)
$rose(pulse) |=> always !pulse);
Ben Cohen
http://www.systemverilog.us/
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- Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2
