Semaphore shared between modules

SystemVerilog
,
1

Is it possible to pass a semaphore to a module as an argument? Thanks.
Ex:

module block_t (logic clk, logic rst, semaphore sem);
....
endmodule

module top_tb;

semaphore sem ();
block_t block_0 (clk, rst, sem);
block_t block_1 (clk, rst, sem);

endmodule
2

In reply to dnguyen82us:

Yes it possible if you follow the right semantics. The default port direction for module ports is inout, and only wires can be connected to inout ports. What you need to do is construct the semaphore at the top level and pass a handle to the semaphore port as inputs to the module.

module block_t (input logic clk, logic rst, semaphore s);
....
endmodule
 
module top_tb;
 
semaphore sem=new();;
block_t block_0 (clk, rst, sem);
block_t block_1 (clk, rst, sem);
 
endmodule
3

In reply to dave_59:

Would this work with generate loop as well, Dave?
Thanks.

module block_t (input logic clk, logic rst, semaphore s);
// Use semaphore before access to a shared bus
// Ex: assign bus = 5;
endmodule

module top_tb;
    semaphore sem = new ();
    genvar port_idx;
    generate
    for (port_idx = 0; port_idx < 8; port_idx++) begin : group
        block_t block (core_clk, core_rst, sem);
    end
endmodule : top_tb
4

In reply to dnguyen82us:

Please use code tags making your code easier to read. I have added them for you.

I do not see why it would not work, but this is not a complete example.