Scalled frequency timing calculations

Hi,
I want an assertion which checks that each clocks should be scaled after 15micrseconds.It should also count the number of clock cycles are scalled and also the clock frequency
thanks,
kani

In reply to kanimozhi:

Need more clarification. What do you mean by scaling?
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In reply to ben@SystemVerilog.us:
Hi,
always @(enable_tb) begin
scale1 =1;
#15 scale2 = 1;
end
In this code I want every 15 cycles after scale1 and scale2 variables should be toggled untill the variable enable_tb =1.
like if first 15 cycles scale1 =1,then after 15 cycles scale1 should go to zero and scale2 should be 1 for 15 cycles.
again after 15 cycles scale2=0 and scale1=1.
this process continues untill enable_tb =1;
if enable_tb =0; then this both scale should be zero

In reply to kanimozhi:
Sorry, but this is the GIGO. I don’t understand the requirements:

always @(enable_tb) begin // The @(enable_tb) is the event that starts the block 
  // This occurs when enable_tb toggles from 1 to 0, or from 0 to 1
  scale1 =1;
  #15 scale2 = 1; // the #15 is a delay 
end

In this code I want every 15 cycles after scale1 and scale2 variables should be toggled untill the variable enable_tb =1.
There is no clock, what cycles are you talking about?
*
like if first 15 cycles scale1 =1,then after 15 cycles scale1 should go to zero and scale2 should be 1 for 15 cycles.
again after 15 cycles scale2=0 and scale1=1.
this process continues untill enable_tb =1;*
??
if enable_tb =0; then this both scale should be zero
But enable_tb toggles.
Hopefully, someone can understand what you mean, but I certainly don’t.
You talk about assertions to check code that makes no sense.