Scalable adapter

SystemVerilog
1

Hi,

How to design a scalable adapter?
Input to that adapter can be 8-bit/16-bit/32-bit and output is of 32-bits.

2

In reply to DhavalP:

Your question is missing a lot of important details. Scalable in what way? Is this for a design or verification? Is it dynamically changeable? Who decides what the input size is? Is there a sampling input/output clock?

3

In reply to dave_59:

Hi Dave,

This can be using system verilog or UVM. Input width should be dynamically changeable.
Is it possible using parametrized class and TLM ports?

4

In reply to DhavalP:

Hi Dave,

There can be sampling input/output clock, too. It is not possible using parameterized class because input is dynamically changed.