Sampling clocking block output

SystemVerilog
1

Hi,

I have an interface as below:


interface my_intf(
  input clk,
  input reset_n,
  inout ready
);

clocking cb_out @ (posedge clk or negedge reset_n);
   output ready;
endclocking

somewhere in my bfm, I would like to sample the ready to do some processing as below
  if(cb_out.ready)
     ............

However, I cannot do that as "sampling clocking block output is prohibited". 

I was wondering if I can have another clocking block declared as below
clocking cb_in @ (posedge clk or negedge reset_n);
   input ready;
endclocking
 
and use it as if(cb_in.ready)....

or

simply declare a signal as below:
logical ready_internal;
assign ready_internal = ready;

and use if(my_intf.ready)..

Does both the methods work? which of these recommended and why? If both of them are not recommended, how do I fix the issue?

Thanks,
Madhu

2

In reply to mseyunni:

There is no point in using a continuous assignment. The recommended approach is using an inout

clocking cb_out @ (posedge clk);
   inout ready;
endclocking

Two separate clocking blocks also works.

Also note that putting
or negedge reset_n in your clocking block event does not work the way you would want.

3

In reply to dave_59:

Thank you Dave.
Could you elaborate on what exactly you meant by “putting or negedge reset_n in your clocking block event does not work the way you would want.”. Sorry, I don’t think I have understood it.

4

In reply to mseyunni:

Unlike what you are used to when writing an always block, a clocking block won’t distinguish between a clock edge and a reset event. what you might want to write instead is

clocking cb_in @ (posedge clk iff (reset_n));

That way the clocking block inputs and outputs are always kept synchronous.

5

In reply to dave_59:

I understand. Thank you Dave.