Runtime change in configuration class

SystemVerilog
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1

How can we change runtime configuration of configuration class?
I’m working on IIS protocol VIP. I took configuration class in environment. Configuration class is having data width, no_transaction, and sampling edge variables. i want to change this configuration values on runtime using single testcase. How can i do it?
(i’m using EDA playground with VCS tool)

2

what I know as per my experience is that configuration class should contain values which are same/constant through out simulation.In UVM, before end_of_elaboration phase, you can configure as per your need. if you want to change something at run time, then you can use run time arguments which are $test$plusargs and $value$plusargs.

3

In reply to juhi_p:

Hi juhi_p,

do you have any example?

4

In reply to K_123:

what exactly you want to do? I can create small example for demonstration.

5

In reply to juhi_p:

Yes, that would be helpful

6

In reply to K_123:

small_uvm_tb - EDA Playground . check here.

7

In reply to juhi_p:

Thanks juhi_p,

actually i’m working on systemverilog (i forgot to tell you earlier) but i’m trying to figure out from your code. and you used $value$plusargs but it works on command line arugument only. if you have any suggestion please tell.

8

In reply to K_123:

What do you mean to say you’re not using UVM? If that’s so then we’re not sure what you mean by configuration class. Can you show us an example?

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In reply to dave_59:

I’m working on i2s protocol VIP using systemverilog.
this is the link of my configuration class. i’m using all this configuration in my transaction, generator and driver.