- $rose(reset) works when there is transition from 0/x/z to 1 and will return true when there is such transition.
- reset without $rose will doesn’t account for transition of 0/x/z to 1 and will return false when there is such transition.
Right?
In reply to abhi9891:
1800’2017: $rose returns true (1’b1) if the LSB of the expression changed to 1. Otherwise, it returns false (1’b0).
Thus, *$rose(reset) works when there is transition from 0/x/z to 1 and will return true when there is such transition.*is a true statement
In reply to ben@SystemVerilog.us:
What about point number 2.
I mean if
example 1. a → reset ##1 b; Does reset return 1 if there is a transition from 0/x/z to 1?
example 2. a → $rose(reset) ##1 b; Here $rose(reset) returns 1 if there is a transition of LSB of reset from 0/x/z to 1.
In reply to abhi9891:
In reply to ben@SystemVerilog.us:
What about point number 2.
I mean if
example 1. a → reset ##1 b; Does reset return 1 if there is a transition from 0/x/z to 1?
All signals are sampled at the Preponed region of the clocking event. Thus, if the sampling of the signal reset==0/x/Z its value is false. If the $past(reset)==0/x/z and the current value is 1, at the current sampling cycle, reset is true.
1800'2017 6.3.1 Logic values
The SystemVerilog value set consists of the following four basic values:
0—represents a logic zero or a false condition
1—represents a logic one or a true condition
x—represents an unknown logic value
z—represents a high-impedance state
1800’2017 Immediate assertions
…
if the expression evaluates to X, Z, or 0, then it is
interpreted as being false, and the assertion statement is said to fail. Otherwise, the expression is interpreted
as being true, and the assertion statement is said to pass or, equivalently, to succeed.
example 2. a → $rose(reset) ##1 b; Here $rose(reset) returns 1 if there is a transition of LSB of reset from 0/x/z to 1.
If the $past(reset)==0/x/z and the current value is 1, at the current sampling cycle, reset is true.
Ben SystemVerilog.us