$rose not working as expected

SystemVerilog
1

I have written the below code:

property tpr_sync_sys_alignment;
@(posedge sysclk)
disable iff ((rst_por_sm != RST_POR_STATE_SYS_READY_DD) | cfg_test_port_dis ) $rose(sysclk) |-> $rose(cgu_sys_clk); endproperty assert_tpr_sync_sys_alignment: assert property (tpr_sync_sys_alignment) else uvm_error(“LCCU_ASSERT_ERROR”,“cgu_sysclk at cgu_soc_wrapper not aligned to sys_clk in tpr mode”)

Other details: sysclk & cgu_sys_clk are same frequency clocks but with different duty cycles.

Problem: My assertions are not getting triggered. All are vacuous.

2

In reply to winkd:

Hi Winkd,

If assertion is passing vacuously , it means that sysclk is not generated.
Kindly show your waveform snapshot to help you further.

3

In reply to het:

I am trying to attach an image, but it’s asking for URL. how to attach an image?

4

In reply to winkd:

Upload it to an image hosting site, such as imgur.

5

In reply to het:

A small self contained example would also help.