I have two interfaces that I would like to call the same driver task with automatic lifetime (so that each interface gets its own copy of the task). It seems like there should be a way to use a package to share the common code. Or is there some other way?
package automatic some_pkg;
automatic logic clk, data;
task drive_data(logic a);
@ (posedge clk);
data = a & data;
endtask
endpackage : some_pkg
interface some_interface0;
import some_pkg::*;
logic if_clk, if_data, b;
assign if_clk = clk; // clk is from some_pkg
assign if_data = data; // data is from some_pkg
initial begin
b = 0;
drive_data(b);
end
endinterface : some_interface0
interface some_interface1;
import some_pkg::*;
logic if_clk, if_data, c;
assign if_clk = clk; // clk is from some_pkg
assign if_data = data; // data is from some_pkg
initial begin
c = 1;
drive_data(c);
end
endinterface : some_interface1
Is this possible in SystemVerilog somehow?