I would like to create a reusable bind module which could be moved to the different hierarchies. More precisely, I mean, inside the bind module wrapper there are several SystemVerilog binds whose bind target scopes could be extended with parameter (or by using something else approach) when the bind wrapper module is moved e.g. from block level to subsystem level. Quite a nasty statement... Anyway the case could be demonstrated as follows:
module #(parameter hier_prefix = "scope") bind_wrapper_module;
bind hier_prefix.reg_bank clk_snoop i_snoop_1 (...);
bind hier_prefix.axi_interconn clk_snoop i_snoop_2 (...);
endmodule : bind_wrapper_module
// Instantiation in block_testbench_top
bind_wrapper_module #("block_testbench_top.i_block") i_bind_wrapper_module();
block i_block (...);
endmodule : block_testbench_top
// Instantiation in subsystem_testbench_top
bind_wrapper_module #("subsystem_testbench_top.i_subsystem.i_block") i_bind_wrapper_module();
subsystem i_subsystem (...);
endmodule : subsystem_testbench_top
As it can be seen, I would like to use parameterization to bind target scope to enable movable wrapper module. I know, obviously, compilers doesn't like that syntax in which parameter is used as part of target scope hierarhy path. Instead, macros would work, but I don't like them. Is there any other workarounds for this case? How you ever done anything like that?
Many thanks for your responses!