Representing an Imaginary Number in SystemVerilog

Hi,
I need to know how do we represent the complex mathematical expression in SystemVerilog.
For eg, consider a number a = 0.707 + j0.707.
Please help me in this, how shall we proceed with the imaginary part.

In reply to venkata-srikanth:

You would typically use a class or struct to define a data type reprising a complex number

class complex_c;
  real Re;
  real Im;
endclass

typedef struct {
  real Re;
  real Im;
} complex_s;

But if you are asking how to represent complex numbers in hardware, that is a much more involved topic since there are only bits in hardware.

Hi Dave, thanks for the response. Can you please suppose you are doing 8 point dif fft verification, and writing scoreboard logic. You did the logic like we used to calculate the fft manually, and you are stuck with the multiplication of twiddle factor.
What would you do?

In reply to venkata-srikanth:

Typically you can find reference models for this kind of operation already written in other languages.

https://www.researchgate.net/publication/334072659_Different_Reference_Models_for_UVM_Environment_to_Speed_Up_the_Verification_Time