In terms of simulation performance, the biggest impact is the creation and sustainability of threads and keeping them active. In reference 1 below, I show A SV implementation of concurrent assertions. Though it is not how simulators really implement assertions, that equivalence has value in that it demonstrates the concepts. Basically, at every successful attempt, you fork a new automatic task, and that task stays in the system until it ends or returns. Here is an example that puts a heavy burden on a simulator:
a[->2] |-> ##[1:2]b; Since a[->2] is equivalent to [a->1] ##1 [a->1], and a[->1] is equivalent to *!a[0:$] ##1 a you have the case where for every “a” (a==0, a==1) you initiate a new living thread that gets terminated only when the consequent passes or fails.
Bottom line, to be efficient in simulation when using assertions, avoid the creation of unnecessary threads as they are equivalent to forked tasks. Also, try to shorten their lifetimes by controlling the test cases.
- VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
- http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
- “Using SVA for scoreboarding and TB designs”
http://systemverilog.us/papers/sva4scoreboarding.pdf - “Assertions Instead of FSMs/logic for Scoreboarding and Verification”
October 2013 | Volume 9, Issue 3 | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
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