Hi All,
Please tell me ,how to implement registers in sv …in uvm we wll go for ral.
please share one register implementation snippet of code in systemverilog register.
using packed arrys /structures ?
Thanks,
Nagendra.
Hi All,
Please tell me ,how to implement registers in sv …in uvm we wll go for ral.
please share one register implementation snippet of code in systemverilog register.
using packed arrys /structures ?
Thanks,
Nagendra.